
Implement in Verilog the following circuit: A D flip-flop takes as input
the output of a two-input XOR. The flip-flop is positive edge triggered
by clk, but there is no reset. The XOR takes as input 'in' along with the
output 'out' of the flip-flop.

module TopModule (
  input clk,
  input in,
  output logic out
);

