
A JK flip-flop has the below truth table. Note: Qold is the output of the
flip-flop before the positive clock edge.

  J | K | Q
  0 | 0 | Qold
  0 | 1 | 0
  1 | 0 | 1
  1 | 1 | ~Qold

module TopModule (
  input clk,
  input j,
  input k,
  output reg Q
);

