
Build an XOR gate three ways, using an assign statement (output
out_assign), a combinational always block (output out_always_comb), and a
clocked always block (output out_always_ff). Note that the clocked always
block produces a different circuit from the other two: There is a flip-
flop so the output is delayed.

module TopModule (
  input clk,
  input a,
  input b,
  output out_assign,
  output reg out_always_comb,
  output reg out_always_ff
);

