
Find the bug and fix this 8-bit wide 2-to-1 mux.

  module top_module (
      input sel,
      input [7:0] a,
      input [7:0] b,
      output out  );

      assign out = (~sel & a) | (sel & b);

  endmodule

module TopModule (
  input sel,
  input [7:0] a,
  input [7:0] b,
  output reg [7:0] out
);

