
For each bit in a 32-bit vector, capture when the input signal changes
from 1 in one clock cycle to 0 the next. "Capture" means that the output
will remain 1 until the register is reset (active high synchronous
reset).

module TopModule (
  input clk,
  input reset,
  input [31:0] in,
  output reg [31:0] out
);

