
A dual-edge triggered flip-flop is triggered on both edges of the clock.
However, FPGAs don't have dual-edge triggered flip-flops, and always
@(posedge clk or negedge clk) is not accepted as a legal sensitivity
list. Build a circuit that functionally behaves like a dual-edge
triggered flip-flop.

module TopModule (
  input clk,
  input d,
  output reg q
);

