
The following diagram is a Mealy machine implementation of the 2's
complementer. Implement in Verilog using one-hot encoding. Resets into
state A and reset is asynchronous active-high.

  A --x=0 (z=0)--> A
  A --x=1 (z=1)--> B
  B --x=0 (z=1)--> B
  B --x=1 (z=0)--> B

module TopModule (
  input clk,
  input areset,
  input x,
  output z
);

