
Consider the state machine shown below:

  A (0) --1--> B
  A (0) --0--> A
  B (0) --1--> C
  B (0) --0--> D
  C (0) --1--> E
  C (0) --0--> D
  D (0) --1--> F
  D (0) --0--> A
  E (1) --1--> E
  E (1) --0--> D
  F (1) --1--> C
  F (1) --0--> D

Assume that a one-hot code is used with the state assignment y[5:0] =
000001(A), 000010(B), 000100(C), 001000(D), 010000(E), 100000(F)

Write a Verilog for the signal Y1, which is the input of state flip-flop
y[1], for the signal Y3, which is the input of state flip-flop y[3].
Derive the Verilog by inspection assuming a one-hot encoding.

module TopModule (
  input [5:0] y,
  input w,
  output Y1,
  output Y3
);

