
This module is a part of the FSM for controlling the shift register, we
want the ability to enable the shift register for exactly 4 clock cycles
whenever the proper bit pattern is detected. Whenever the FSM is reset,
assert shift_ena for 4 cycles, then 0 forever (until reset). Reset should
be active high synchronous.

module TopModule (
  input clk,
  input reset,
  output shift_ena
);

