
Consider the state machine shown below:

  A (0) --0--> B
  A (0) --1--> A
  B (0) --0--> C
  B (0) --1--> D
  C (0) --0--> E
  C (0) --1--> D
  D (0) --0--> F
  D (0) --1--> A
  E (1) --0--> E
  E (1) --1--> D
  F (1) --0--> C
  F (1) --1--> D

Resets into state A. For this part, assume that a one-hot code is used
with the state assignment y[6:1] = 000001, 000010, 000100, 001000,
010000, 100000 for states A, B,..., F, respectively.

Write Verilog for the next-state signals Y2 and Y4 corresponding to
signal y[2] and y[4]. Derive the logic equations by inspection assuming a
one-hot encoding.

module TopModule (
  input [6:1] y,
  input w,
  output Y2,
  output Y4
);

