
Consider the follow Moore machine with the diagram described below:

  B (1) --0--> A
  B (1) --1--> B
  A (0) --0--> B
  A (0) --1--> A

Write Verilog implementing this state machine. It should asynchronously
reset into state B if reset if high.

module TopModule (
  input clk,
  input in,
  input areset,
  output out
);

