
This is a Moore state machine with two states, two inputs, and one
output. Implement this state machine in Verilog. Reset is an active-high
synchronous reset to state OFF.

  OFF (out=0) --j=0--> OFF
  OFF (out=0) --j=1--> ON
  ON  (out=1) --k=0--> ON
  ON  (out=1) --k=1--> OFF

module TopModule (
  input clk,
  input j,
  input k,
  input reset,
  output out
);

