
Given the state-assigned table shown below, implement the finite-state
machine. Reset should synchronous active high reset the FSM to state 000.

  Present state y[2:0] | Next state y[2:0] x=0, Next state y[2:0] x=1 | Output z
  000 | 000, 001 | 0
  001 | 001, 100 | 0
  010 | 010, 001 | 0
  011 | 001, 010 | 1
  100 | 011, 100 | 1

module TopModule (
  input clk,
  input reset,
  input x,
  output reg z
);

