
Consider the FSM described by the state diagram shown below:

  A --r1=0,r2=0,r3=0--> A
  A --r1=1--> B
  A --r1=0,r2=1--> C
  A --r1=0,r2=0,r3=0--> D
  B (g1=1) --r1=1--> B
  B (g1=1) --r1=0--> A
  C (g2=1) --r2=1--> C
  C (g2=1) --r2=0--> A

Resetn is an active-low synchronous reset that resets into state A. This
FSM acts as an arbiter circuit, which controls access to some type of
resource by three requesting devices. Each device makes its request for
the resource by setting a signal _r[i]_ = 1, where _r[i]_ is either
_r[1]_, _r[2]_, or _r[3]_. Each r[i] is an input signal to the FSM, and
represents one of the three devices. The FSM stays in state _A_ as long
as there are no requests. When one or more request occurs, then the FSM
decides which device receives a grant to use the resource and changes to
a state that sets that device's _g[i]_ signal to 1. Each _g[i]_ is an
output from the FSM. There is a priority system, in that device 1 has a
higher priority than device 2, and device 3 has the lowest priority.
Hence, for example, device 3 will only receive a grant if it is the only
device making a request when the FSM is in state _A_. Once a device, _i_,
is given a grant by the FSM, that device continues to receive the grant
as long as its request, _r[i]_ = 1.

Write complete Verilog code that represents this FSM. Use separate always
blocks for the state table and the state flip-flops, as done in lectures.
Describe the FSM outputs, _g[i]_, using either continuous assignment
statement(s) or an always block (at your discretion). Assign any state
codes that you wish to use.

module TopModule (
  input clk,
  input resetn,
  input [3:1] r,
  output [3:1] g
);

