
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.

 - input  in1
 - input  in2
 - output out

The module should implement the following circuit in Verilog. Two inputs
(in1 and in2) go to an AND gate, but the in2 input to the AND gate has a
bubble. The output of the AND gate is connected to 'out'.

