
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.

 - input  clk
 - input  resetn
 - input  in
 - output out

The module should implement a shift register with four D flops. Assume
all sequential logic is triggered on the positive edge of the clock.
Reset is active-low synchronous resettable.

