
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.

 - input  clk
 - input  reset
 - input  in
 - output out

Implement the following Moore state machine with two states, one input,
and one output. The reset state is B and reset is active-high
synchronous.

  B (out=1) --in=0--> A
  B (out=1) --in=1--> B
  A (out=0) --in=0--> B
  A (out=0) --in=1--> A

