
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.

 - input  clk
 - input  reset
 - input  data
 - input  done_counting
 - input  ack
 - output shift_ena
 - output counting
 - output done

The module should implement a timer that:

  (1) is started when a particular pattern (1101) is detected,
  (2) shifts in 4 more bits to determine the duration to delay,
  (3) waits for the counters to finish counting, and
  (4) notifies the user and waits for the user to acknowledge the timer.

In this problem, implement just the finite-state machine that controls
the timer. The data path (counters and some comparators) are not included
here.

The serial data is available on the data input pin. When the pattern 1101
is received, the state machine must then assert output shift_ena for
exactly 4 clock cycles. After that, the state machine asserts its
counting output to indicate it is waiting for the counters, and waits
until input done_counting is high.At that point, the state machine must
assert done to notify the user the timer has timed out, and waits until
input ack is 1 before being reset to look for the next occurrence of the
start sequence (1101). The state machine should have a active high
synchronous reset, setting the state to where it begins searching for the
input sequence 1101. Assume all sequential logic is triggered on the
positive edge of the clock.

