// Implement the Verilog module based on the following description. Assume that signals are positive clock/clk triggered unless otherwise stated.
//
// The module should implement an incrementer which increments the input by
// one and writes the result to the output. Assume all values are encoded as
// two's complement binary numbers.

module TopModule
(
  input  logic [7:0] in_,
  output logic [7:0] out
);

  // Combinational logic

  assign out = in_ + 1;

endmodule
